The semiconductor industry is constantly seeking ways to reduce the dimensions of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). Modern semiconductor processing technologies are typically defined by the minimum feature size (e.g. channel width) of the devices. Smaller feature sizes provide faster switching speeds and allow for more semiconductor devices to be produced in a smaller area, thus reducing production costs.
The need to reduce device dimensions correspondingly leads to a need to manufacture smaller scale trenches in semiconductors. Many semiconductor devices utilize a trench design. For example, a gate electrode of a transistor may be provided in a trench, beneath a surface of a semiconductor material. The benefits of this trench design may include increased current-carrying capacity and increased reverse voltage blocking capability, which may be particularly advantageous in high power applications. Additionally, trenches are commonly used to provide electrical contacts to device regions, such as a source or body contact.
Narrow and high aspect ratio trenches enable the manufacture of smaller, higher performance devices and enable further scaling of processing technologies. Leading-edge technologies may require trench widths as narrow as a few tens of nanometers. These dimensions may be beyond the resolution of modern photolithography techniques, or may only be possible at reduced yield. Additional challenges arise if a device design requires two differently dimensioned trenches spaced close to one another (e.g. a gate trench arranged next to a source contact trench). Conventional lithography can only achieve these differently dimensioned trenches by separate masking and etching steps for each trench, which increases cost and reduces yield.